ACT8810(2009) Ver la hoja de datos (PDF) - Active-Semi, Inc
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ACT8810 Datasheet PDF : 52 Pages
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Active-Semi
ACT8810
Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
Sequence B
The ACT8810QJ2## which is set with “sequence
B“, has a system startup is initiated whenever the
following conditions occurs:
1) nPBIN is pushed low via 100kΩ resistance,
When ever this condition exists, the
ACT8810QJ2## begins its system startup
procedure by enabling REG1. When REG1 reaches
94% of its final regulation voltage, ACT8810QJ2##
automatically turns on REG2 and REG3 and
nRSTO is asserted low, holding the microprocessor
in reset for a user-selectable reset period of 260ms.
If VOUT1 is within 6% of its regulation voltage when
the reset timer expires, the nRSTO is de-asserted,
and the microprocessor can begin its power-up
sequence. Once the power-up routine is
successfully completed, the system remains
enabled after the push-button is released as long as
the microprocessor asserts any one of ON1, ON2
or ON3. REG4 and REG5 may be enabled if the
microprocessor sets REG4.ON[] and REG5.ON[] to
1 via the I2C interface. In other case, REG4 and
REG5 are disable.
This start-up procedure requires that the
pushbutton be held until the microprocessor
assumes control (by asserting any one of ON1,
ON2, and ON3), providing protection against
inadvertent momentary assertions of the
pushbutton. If desired, longer “push-and-hold” times
can be easily implemented by simply adding an
additional time delay before asserting ON1, ON2, or
ON3. If the microprocessor is unable to complete its
power-up routine successfully before the user lets
go of the push-button, the ACT8810QJ2##
automatically shuts itself down.
Figure 4:
Sequence B
First Push
Button
Assert Release
Power-Hold Button
Second Push System
Button Shutdown
nPBIN
System Enable
OUT1
Enable Qualification
ON1, ON2, ON3
OUT2, OUT3
REG4.ON[ ],
REG5.ON[ ]
OUT4, OUT5
Reset time Enable
nRSTO
nIRQ
94% of VOUT1
~100ms
260ms
Sequence C
The ACT8810QJ3## which is set with “sequence
C“, has a system startup is initiated whenever the
following conditions occurs:
1) nPBIN is pushed low via 100kΩ resistance,
When ever this condition exists, the
ACT8810QJ3## begins its system startup
procedure by enabling REG1. When REG1 reaches
94% of its final regulation voltage, ACT8810QJ3##
automatically turns on REG2, REG3, REG4, REG5
and nRSTO is asserted low, holding the
microprocessor in reset for a user-selectable reset
period of 260ms. If VOUT1 is within 6% of its
regulation voltage when the reset timer expires, the
nRSTO is de-asserted, and the microprocessor can
begin its power-up sequence. Once the power-up
routine is successfully completed, the system
remains enabled after the push-button is released
as long as the microprocessor asserts any one of
ON1, ON2 or ON3, and REG4, REG5 may be
enabled or disabled via the I2C interface.
This start-up procedure requires that the
pushbutton be held until the microprocessor
assumes control (by asserting any one of ON1,
ON2, and ON3), providing protection against
inadvertent momentary assertions of the
pushbutton. If desired, longer “push-and-hold” times
can be easily implemented by simply adding an
additional time delay before asserting ON1, ON2, or
ON3. If the microprocessor is unable to complete its
power-up routine successfully before the user lets
go of the push-button, the ACT8810QJ3##
automatically shuts itself down.
Figure 5:
Sequence C
First Push
Button
nPBIN
Assert
Release
Power-Hold Button
Second Push System
Button Shutdown
System Enable
OUT1
Enable Qualification
ON1, ON2, ON3
OUT2, OUT3
OUT4, OUT5
Reset time Enable
nRSTO
nIRQ
94% of VOUT1
~100ms
260ms
Innovative PowerTM
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
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www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
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