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ACT8810QJ213-T Datasheet PDF : 54 Pages
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ACT8810
Rev 9, 15-Nov-12
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTION
General Description
The ACT8810 offers a wide array of system
management functions that allow it to be configured
for optimal performance in a wide range of
applications.
I2C Serial Interface
At the core of the ACT8810’s flexible architecture is
an I2C interface that permits optional programming
capability to enhance overall system performance.
To ensure compatibility with a wide range of system
processors, the ACT8810 uses standard I2C
commands; I2C write-byte commands are used to
program the ACT8810, and I2C read-byte
commands are used to read the ACT8810’s internal
registers. The ACT8810 always operates as a slave
device, and is addressed using a 7-bit slave
address followed by an eighth bit, which indicates
whether the transaction is a read-operation or a
write-operation, [1011010x].
SDA is a bi-directional data line and SCL is a clock
input. The master initiates a transaction by issuing a
START condition, defined by SDA transitioning from
high to low while SCL is high. Data is transferred in
8-bit packets, beginning with the MSB, and is
clocked-in on the rising edge of SCL. Each packet
of data is followed by an “Acknowledge” (ACK) bit,
used to confirm that the data was transmitted
successfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com
System Startup and Shutdown
Startup Sequence
The ACT8810 features a flexible enable
architecture that allows it to support a variety of
push-button enable/disable schemes. Although
other startup routines are possible, ACT8810
provides three typical startup and shutdown
processes proceed as shown in Control Sequence
section.
process is completely software-controlled, a typical
shutdown sequence proceeds as follows: The
second assertion of nPBIN asserts nPBIN and
interrupts the microprocessor, which then initiates
an interrupt service routine to reveal that nPBIN has
been asserted. If there is no input to the charger,
then the microprocessor disables each regulator
according to the sequencing requirements of the
system, then the system will finally be disabled
when each of ON1, ON2, and ON3 have been de-
asserted.
nPBIN Input
ACT8810's nPBIN pin is a dual-function pin,
combining system enable/disable control with a
hardware reset function. Refering to Figure 2, the
two pin functions are obtained by asserting this pin
low, either through a direct connection or through a
100kΩ resistor, as described below.
In most applications, nPBIN will be driven through a
100kΩ resistor. When driven in this way, nPBIN
initiates system startup or shutdown, as described
in the System Startup and Shutdown section.
When a hardware-reset function is desired, nPBIN
may also be driven directly to GA. In this case,
nRSTO is immediately asserted low and remains
low until nPBIN is de-asserted and the reset timeout
period expires. This provides a hardware-reset
function, allowing the system to be manually reset if
the system processor locks up.
Although a typical application will use momentary
switches to drive nPBIN, as shown in Figure 2,
nPBIN may also be driven by other sources, such
as a GPIO or other logic output.
Figure 2:
nPBIN Input
Shutdown Sequence
Once a successful power-up routine is completed, a
shutdown process may be initiated by asserting
nPBIN a second time, typically as the result of
pressing the push-button. Although the shutdown
Enable/Disable Inputs (ON1, ON2 and ON3)
The ACT8810 provides three manual
enable/disable inputs, ON1, ON2 and ON3, which
Innovative PowerTM
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2012 Active-Semi, Inc.
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