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ACT8810QJ3EB-T

Eight Channel ActivePath™ Power Management IC

Active-Semi, Inc 

ACT8810

Rev 9, 15-Nov-12

SYSTEM MANAGEMENT

FUNCTIONAL DESCRIPTION CONT’D

enable and disable REG1, REG2, and REG3,

respectively. Once the system is enabled, the

system will remain enabled until all of ON1, ON2,

and ON3 have been de-asserted. See the Control

Sequence section for more information.

Power-On Reset Output

nRSTO is an open-drain output which asserts low

upon startup or when nPBIN is driven directly to

GA, and remains asserted low until the 260ms

(default) power-on reset timer has expired. Connect

a 10kΩ or greater pull-up resistor from nRSTO to an

appropriate voltage supply.

nIRQ Output

nIRQ is an open-drain output that asserts low any

time startup or an unmasked fault condition exists.

When asserted, nIRQ remains low until the

microprocessor polls the ACT8810's I2C interface.

The ACT8810 supports a variety of other fault

conditions, which may each be optionally unmasked

via the I2C interface. For more information about the

available fault conditions, refer to the appropriate

sections of this datasheet.

Connect a pull-up resistor from nIRQ to an

appropriate voltage supply. nIRQ is typically used to

drive the interrupt input of the system processor,

and is useful in a variety of software-controlled

enable/disable control routines.

Thermal Shutdown

The ACT8810 integrates thermal shutdown

protection circuitry to prevent damage resulting

from excessive thermal stress, as may be

encountered under fault conditions. This circuitry

disables all regulators if the ACT8810 die

temperature exceeds 160°C, and prevents the

regulators from being enabled until the IC

temperature drops by 20°C (typ).

Control Sequence

Sequence A

The ACT8810QJ1## which is set with “sequence

A“, has a system startup is initiated whenever the

following conditions occurs:

1) nPBIN is pushed low via 100kΩ resistance,

When ever this condition exists, the

ACT8810QJ1## begins its system startup

procedure by enabling REG1. When REG1 reaches

94% of its final regulation voltage, ACT8810QJ1##

automatically turns on REG4 and REG5 and

nRSTO is asserted low, holding the microprocessor

in reset for a user-selectable reset period of 260ms.

If VOUT1 is within 6% of its regulation voltage when

the reset timer expires, the nRSTO is de-asserted,

and the microprocessor can begin its power-up

sequence. Once the power-up routine is

successfully completed, the system remains

enabled after the push-button is released as long as

the microprocessor asserts any one of ON1, ON2

or ON3, and REG4, REG5 may be enabled or

disabled via the I2C interface.

This start-up procedure requires that the

pushbutton be held until the microprocessor

assumes control (by asserting any one of ON1,

ON2, and ON3), providing protection against

inadvertent momentary assertions of the

pushbutton. If desired, longer “push-and-hold” times

can be easily implemented by simply adding an

additional time delay before asserting ON1, ON2, or

ON3. If the microprocessor is unable to complete its

power-up routine successfully before the user lets

go of the push-button, the ACT8810QJ1##

automatically shuts itself down.

Figure 3:

Sequence A

First Push

Button

nPBIN

Assert Release

Power-Hold Button

Second Push System

Button Shutdown

System Enable

OUT1

ON1, ON2, ON3

OUT2, OUT3

OUT4, OUT5

Reset time Enable

nRSTO

nIRQ

94% of VOUT1

260ms

Innovative PowerTM

ActivePMUTM and ActivePathTM are trademarks of Active-Semi.

I2CTM is a trademark of NXP.

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www.active-semi.com

Copyright © 2012 Active-Semi, Inc.

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