AD5445BCP(2002) Ver la hoja de datos (PDF) - Analog Devices
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AD5445BCP
(Rev.:2002)
(Rev.:2002)
Analog Devices
AD5445BCP Datasheet PDF : 12 Pages
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PRELIMINARY TECHNICAL DATA
Single Supply Operation (Biased Mode)
AD5424/AD5433/AD5445
(VDD = 2.5 V to 5.5 V, VREF = +2 V, IOUT2 = 1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177,
AC performance with AD811 unless otherwise noted.)
Parameter
STATIC PERFORMANCE
AD5424
Resolution
Relative Accuracy
Differential Nonlinearity
AD5433
Resolution
Relative Accuracy
Differential Nonlinearity
AD5445
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temp Coefficient2
Output Leakage Current
Min
Typ
±5
Output Voltage Compliance Range
REFERENCE INPUT2
Reference Input Range
VREF Input Resistance
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIL
Input Capacitance
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
DYNAMIC PERFORMANCE2
Reference Multiplying BW
Output Voltage Settling Time
AD5424
AD5433
AD5445
Slew Rate
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
TBD
tbd
8
10
1.7
VDD - 1
VDD - 0.5
10
TBD
15
22
30
100
3
Output Capacitance
Digital Feedthrough
5
Total Harmonic Distortion
Output Noise Spectral Density
SFDR performance
Intermodulation Distortion
-85
-85
25
72
TBD
POWER REQUIREMENTS
Power Supply Range
2.5
IDD
Power Supply Sensitivity2
NOTES
1Temperature range is as follows: B Version: –40°C to +105°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
Max
8
±0.5
±1
10
±1
±1
12
±2
±1
±2
±10
±50
12
0.8
0.7
1
10
0.4
0.4
TBD
TBD
TBD
-75
2
4
5.5
10
0.001
Units
Conditions
Bits
LSB
LSB
Guaranteed Monotonic
Bits
LSB
LSB
Guaranteed Monotonic
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
V
Guaranteed Monotonic
Data = 0000H, TA = 25°C, IOUT1
Data = 0000H, IOUT1
V
kΩ
Input resistance TC = -50ppm/°C
V
V
V
µA
pF
V
V
V
V
MHz
MHz
ns
ns
ns
V/µs
nV-s
dB
pF
pF
nV-s
dB
dB
nV/√Hz
dB
dB
VDD = 2.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
ISINK = 200 µA
ISOURCE = 200 µA
ISINK = 200 µA
ISOURCE = 200 µA
VREF = 100 mV rms, DAC loaded all 1s
VREF = 1 V rms, DAC loaded all 1s
Measured to ½ LSB. RLOAD = 100Ω, CLOAD =
15pF. DAC latch alternately loaded with
0s and 1s.
1 LSB change around Major Carry
DAC latch loaded with all 0s. Reference =
10kHz.
DAC Latches Loaded with all 0s
DAC Latches Loaded with all 1s
Feedthrough to DAC output with CS high
and Alternate Loading of all 0s and all 1s.
VREF = 2 Vp-p, 1V Bias, All 1s loaded, f = 1kHz
VREF = 2 V, Sinewave generated from digital code.
@ 1kHz
V
µA
%/%
Logic Inputs = 0 V or VDD
∆VDD = ±5%
–3–
REV. PrH
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