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AOZ1010

2A Simple Buck Regulator

Alpha and Omega Semiconductor 

AOZ1010

The junction to ambient temperature can be got from

power dissipation in the AOZ1010 and thermal imped-

ance from junction to ambient.

T (jun-amb) = (Ptotalloss–Pinductorloss) × ΘJA

The maximum junction temperature of AOZ1010 is

145°C, which limits the maximum load current capability.

Please see the thermal de-rating curves for the maximum

load current of the AOZ1010 under different ambient

temperatures.

The thermal performance of the AOZ1010 is strongly

affected by the PCB layout. Extra care should be taken

by users during the design process to ensure that the IC

will operate under the recommended environmental

conditions.

Several layout tips are listed below for the best electric

and thermal performance. Figure 3 below illustrates a

single layer PCB layout example as a reference.

1. Do not use thermal relief connection to the VIN and

the PGND pin. Pour a maximized copper area to

the PGND pin and the VIN pin to help thermal

dissipation.

2. Input capacitor should be connected to the VIN pin

and the PGND pin as close as possible.

3. A ground plane is preferred. If a ground plane is not

used, separate PGND from AGND and connect them

only at one point to avoid the PGND pin noise

coupling to the AGND pin. In this case, a decoupling

capacitor should be connected between VIN pin and

AGND pin.

4. Make the current trace from LX pins to L to Co to the

PGND as short as possible.

5. Pour copper plane on all unused board area and

connect it to stable DC nodes, like VIN, GND, or VOUT.

6. The two LX pins are connected to the internal PFET

drain. They are low resistance thermal conduction

path and most noisy switching node. Connect a

copper plane to the LX pin to help thermal

dissipation. This copper plane should not be too

large otherwise switching noise may be coupled to

other parts of the circuit.

7. Keep sensitive signal traces such as trace connect-

ing FB pin and COMP pin away from the LX pins.

Cin PGND 1

8

VIN 2 SO-8 7

Cd

AGND 3

6

R2

FB

4

5

R1

Cc Rc

LX Cout

LX L

EN

COMP

Figure 3. AOZ1010 PCB Layout

Rev. 1.0 November 2006

www.aosmd.com

Page 11 of 14

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