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BD37A19F

Voltage Detector ICs with Watchdog Timer

ROHM Semiconductor 

BD37Axx Series BD87Axx Series BD99A41F

Datasheet

8) Ground Wiring Pattern

When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,

placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage

variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change

the GND wiring pattern of any external components, either.

9) Applications or inspection processes with modes where the potentials of the VDD pin and other pins may be reversed

from their normal states may cause damage to the IC’s internal circuitry or elements. Use an output pin capacitance of

1000 µF or lower in case VDD is shorted with the GND pin while the external capacitor is charged. It is recommended to

insert a diode for preventing back current flow in series with VDD or bypass diodes between Vcc and each pin.

Back current prevention diode

Bypass diode

VDD Pin

Figure 19.

10) When VDD falls below the operating marginal voltage, output will be open. When output is being pulled up to input,

output will be equivalent to VDD.

11) Input pin

The CLK and INH pins comprise inverter gates and should not be left open. (These pins should be either pulled up or

down.) Input to the CLK pin is detected using a positive edge trigger and does not affect the CLK signal duty. Input the

trigger to the CLK pin within the TWH time.

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TSZ22111・15・001

11/15

TSZ02201-0T2T0AN00130-1-2

25.Apr.2013 Rev.002

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