CS48DV2B-DQZ(2008) Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

componentes Descripción

Lista de partido

CS48DV2B-DQZ
(Rev.:2008)

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

Cirrus Logic 

CS48DV2B Data Sheet

32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby

5.15 Switching Characteristics — Digital Audio Output Port

Parameter

Symbol

Min

Max

Unit

DAO_MCLK period

DAO_MCLK duty cycle

DAO_SCLK period for Master or Slave mode1

DAO_SCLK duty cycle for Master or Slave mode1

Tdaomclk

40

-

45

Tdaosclk

40

-

40

-

ns

55

%

-

ns

60

%

Master Mode (Output A1 Mode)1,2

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input

tdaomsck

-

DAO_LRCLK delay from DAO_SCLK transition, respectively3

tdaomstlr

-

T DAO_SCLK delay from DAO_LRCLK transition, respectively3

tdaomlrts

-

DAO1_DATA[3..0], DAO2_DATA[1..0]

F delay from DAO_SCLK transition3

tdaomdv

-

Slave Mode (Output A0 Mode)4

19

ns

8

ns

8

ns

10

ns

A DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK transition3

tdaosdv

-

R DAO_LRCLK delay from DAO_SCLK transition, respectively3

tdaosstlr

-

D DAO_SCLK delay from DAO_LRCLK transition, respectively3

tdaoslrts

-

15

ns

30

ns

15

ns

1. Master mode timing specifications are characterized, not production tested.

2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce

L I DAO_SCLK, DAO_LRCLK.

3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the

data is valid.

IA H 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

NT LP DAO_MCLK

IDE DE DAO_SCLK

tdaomdv

F DAOn_DATAn

CON DAO_LRCLK

tdaomlclk

tdaomsck

DAO_MCLK

DAO_SCLK

tdaomlrts

DAOn_DATAn

DAO_LRCLK

tdaomclk

tdaomsck

tdaomstlr

Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

DS875F1

Copyright 2008 Cirrus Logic

19

CONFIDENTIAL

Share Link: