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CX82100-51

Home Network Processor (HNP)

Conexant Systems 

CX82100 Home Network Processor Data Sheet

5 Host Interface Description ................................................................................................................... 5-1

5.1 Master Mode ...............................................................................................................................................................5-1

5.1.1 Host Master Mode Interface Signals ............................................................................................................5-1

5.1.2 Flash Memory Interface ...............................................................................................................................5-3

5.1.3 Interfacing to Other Slave Devices ...............................................................................................................5-3

5.1.4 Host Master Mode DMA Engine...................................................................................................................5-3

Asynchronous DMA Transfer Mode .....................................................................................................5-3

Isochronous DMA Transfer Mode ........................................................................................................5-3

5.1.5

General DMA Information ....................................................................................................................5-4

Host Master Mode Timing (CX82100-11/-12/-51/-52) .................................................................................5-5

Host Master Mode Read Operation (Accessing an External Device) .....................................................5-5

5.1.6

Host Master Mode Write Operation (Accessing an External Device) .....................................................5-5

Host Master Mode Timing (CX82100-41/-42)..............................................................................................5-8

Host Master Mode Read Operation (Accessing an External Device) .....................................................5-8

Host Master Mode Write Operation (Accessing an External Device) .....................................................5-8

HRDY# Description (CX82100-41/-42) ................................................................................................5-9

5.2 Host Master Mode Register Memory Map .................................................................................................................5-12

5.3 Host Master Mode Registers .....................................................................................................................................5-13

5.3.1 Host Control Register (HST_CTRL: 0x002D0000)......................................................................................5-13

5.3.2 Host Master Mode Read-Wait-State Control Register (HST_RWST: 0x002D0004) ....................................5-14

5.3.3 Host Master Mode Write-Wait-State Control Register) (HST_WWST: 0x002D0008)..................................5-14

5.3.4 Host Master Mode Transfer Control Register (HST_XFER_CNTL: 0x002D000C)........................................5-14

5.3.5 Host Master Mode Read Control Register 1 (HST_READ_CNTL1: 0x002D0010) .......................................5-14

5.3.6 Host Master Mode Read Control Register 2 (HST_READ_CNTL2: 0x002D0014) .......................................5-15

5.3.7 Host Master Mode Write Control Register 1 (HST_WRITE_CNTL1: 0x002D0018) .....................................5-15

5.3.8 Host Master Mode Write Control Register 2 (HST_WRITE_CNTL2: 0x002D001C).....................................5-15

5.3.9 Host Master Mode Peripheral Size (MSTR_INTF_WIDTH: 0x002D0020) ...................................................5-15

5.3.10 Host Master Mode Peripheral Handshake (MSTR_HANDSHAKE: 0x002D0024) (CX82100-41/-42) ...........5-16

5.3.11 Host Master Mode DMA Source Address (HDMA_SRC_ADDR: 0x002D0028)...........................................5-16

5.3.12 Host Master Mode DMA Destination Address (HDMA_DST_ADDR: 0x002D002C) ....................................5-16

5.3.13 Host Master Mode DMA Byte Count (HDMA_BCNT: 0x002D0030) ............................................................5-16

5.3.14 Host Master Mode DMA Timers (HDMA_TIMERS: 0x002D0034) ..............................................................5-16

6 External Memory Controller Interface Description ............................................................................... 6-1

6.1 PC100 Compliant SDRAM Interface.............................................................................................................................6-1

6.2 Available Vendor SDRAM ICs and Features .................................................................................................................6-3

6.3 Supported Configurations............................................................................................................................................6-4

6.4 Access Cycles .............................................................................................................................................................6-4

6.5 Initialization.................................................................................................................................................................6-4

6.6 Refresh .......................................................................................................................................................................6-4

6.7 Read............................................................................................................................................................................6-5

6.8 Write ...........................................................................................................................................................................6-5

6.9 Throughput .................................................................................................................................................................6-5

6.10 EMC I/O Clock Interface and Timing ............................................................................................................................6-6

6.11 SRAM Interface ...........................................................................................................................................................6-7

6.12 EMC Register ..............................................................................................................................................................6-8

6.12.1 External Memory Control Register (EMCR: 0x00350010) ............................................................................6-8

101306C

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