DM9161A Ver la hoja de datos (PDF) - Unspecified

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DM9161A

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

Unspecified 

5.2 Media Interface, 4 pins

Pin No.

3,4

7,8

Pin Name

RX+

RX-

TX+

TX-

5.3 LED Interface, 3 pins

Pin No.

11

Pin Name

LED0

/OP0

12

LED1

/OP1

13

LED2

/OP2

5.4 Mode, 3 pins

Pin No.

10

Pin Name

PWRDWN

14

CABLESTS

/LINKSTS

39

DISMDIX

I/O

Description

I Differential Receive Pair

Differential data is received from the media

O Differential Transmit Pair/PECL Transmit Pair

Differential data is transmitted to the media in TP mode

I/O

Description

O, LED Driver output 0

LI OP0: (power up reset latch input)

(U) This pin is used to control the forced or advertised operating mode of the

DM9161A according to the Table A. The value is latched into the

DM9161A registers at power-up/reset

O,

LI LED Driver output 1

(U) OP1: (power up reset latch input)

This pin is used to control the forced or advertised operating mode of the

DM9161A according to the Table A. The value is latched into the

DM9161A registers at power-up/reset

O, LED Driver output 2

LI OP2: (power up reset latch input)

(U) This pin is used to control the forced or advertised operating mode of the

DM9161A according to the Table A. The value is latched into the

DM9161A registers at power-up/reset

I/O

Description

I Power Down Control

Asserted high to force the DM9161A into power down mode. When in

power down mode, most of the DM9161A circuit block’s power is turned

off, only the MII management interface (MDC, MDIO) logic is available

(the PHY should respond to management transactions and should not

generate spurious signals on the MII)). To leave power down mode, the

DM9161A needs the hardware or software reset with the PWRDWN pin

low

O, Cable Status or Link Status

LI This pin is used to indicate the status of the cable connection when

(D) power up reset latch low (Default)

0 = Without cable connection

1 = With cable connection

This pin is used to indicate the status of the Link connection when power

up reset latch high

0 = With link

1 = Without link

I Auto MDIX Control

(D) 1: Disable auto mode

0: Enable auto MDI/MDIX mode

5.5 Bias and Clock, 4 pins

Preliminary

8

Version: DM9161A-DS-P04

Jan.19, 2005

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