EBE21FD4AGFN-5C-E Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EBE21FD4AGFN-5C-E

2GB Fully Buffered DIMM

Elpida Memory, Inc 

EBE21FD4AGFD, EBE21FD4AGFN

High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces

The AMB supports one FB-DIMM channel consisting of two bidirectional link interfaces using high-speed differential

point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data

from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards

this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or

status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards

this information back towards the host and multiplexes in any read return data or status information that is generated

internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs.

Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and

commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary

differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound

on 14 secondary differential pairs.

DDR2 Channel

The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two

ranks of eight banks with 16 row/column request, 64 data, and eight check-bit signals. There are two copies of

address and command signals to support DIMM routing and electrical requirements. Four transfer bursts are driven

on the data and check-bit lines at 800MHz. Propagation delays between read data/check-bit strobe lanes on a given

channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error.

Hardware aligns the read data and check-bits to a single core clock. The AMB provides four copies of the command

clock phase references (CLK [3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble.

SMBus Slave interface

The AMB supports an SMBus interface to allow system access to configuration register independent of the FB-DIMM

link. The AMB will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at

100kHz. SMBus access to the AMB may be a requirement to boot and to set link strength, frequency and other

parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down.

The SMBus address straps located on the DIMM connector are used by the unique ID.

Preliminary Data Sheet E0868E30 (Ver. 3.0)

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