IDT70P248L(2009) Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT70P248L
(Rev.:2009)
(Rev.:2009)
Integrated Device Technology
IDT70P248L Datasheet PDF : 23 Pages
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IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
70P258/248
Ind'l Only
Symbol
Parameter
Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
55
____
ns
45
____
ns
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
45
____
ns
0
____
ns
tWP
Write Pulse Width
40
____
ns
tWR
Write Recovery Time
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(1,2)
tDH
Data Hold Time(4)
tWZ
Write Enable to Output in High-Z(1,2)
tOW
Output Active from End-of-Write(1,2,4)
30
____
ns
____
25
ns
0
____
ns
____
25
ns
0
____
ns
tSWRD
SEM Flag Write to Read Time
10
____
ns
tSPS
SEM Flag Contention Window
10
____
ns
NOTES:
5675 tbl 12
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
61.402
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