IDT70P248L Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT70P248L Datasheet PDF : 23 Pages
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IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
ADDRESS
OE
(9)
CE or SEM
tWC
tAW
tHZ (7)
CE or SEM(9)
R/W
DATAOUT
DATAIN
tAS (6)
tWP (2)
tWZ (7)
(4)
tDW
tWR(3)
tOW
tDH
(4)
,
5675 drw 06
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
ADDRESS
CE or SEM (9)
tWC
tAW
UB or LB(9)
tAS(6)
tEW (2)
tWR(3)
R/W
tDW
tDH
DATAIN
,,
5675 drw 07
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W going HIGH (or SEM going LOW) to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
Test Load.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
61.412
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