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74ALVT162823

18-bit bus-interface D-type flip-flop with reset and enable with 30Ω termination resistors (3-State)

Philips Electronics 

Philips Semiconductors

2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset

and enable with 30Ω termination resistors (3-State)

Product specification

74ALVT162823

FEATURES

• Two sets of high speed parallel registers with positive

edge-triggered D-type flip-flops

• 5V I/O Compatible

• Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

• Live insertion/extraction permitted

• Power-up 3-State

• Power-up Reset

• Output capability: +12mA/–12mA

• Latch-up protection exceeds 500mA per Jedec Std 17

• ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

• Bus hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

• Outputs include series resistance of 30Ω making external

termination resistors unnecessary

DESCRIPTION

The 74ALVT162823 18-bit bus interface register is designed to

eliminate the extra packages required to buffer existing registers and

provide extra data width for wider data/address paths of buses

carrying parity.

The 74ALVT162823 has two 9-bit wide buffered registers with Clock

Enable (nCE) and Master Reset (nMR) which are ideal for parity bus

interfacing in high microprogrammed systems.

The registers are fully edge-triggered. The state of each D input, one

set-up time before the Low-to-High clock transition is transferred to

the corresponding flip-flop’s Q output.

The 74ALVT162823 is designed with 30Ω series resistance in both

the pull-up and pull-down output structures. This design reduces line

noise in applications such as memory address drivers, clock drivers,

and bus receivers/transmitters.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

tPLH

tPHL

CIN

COUT

ICCZ

Propagation delay

nCP to nQx

Input capacitance

Output capacitance

Total supply current

CONDITIONS

Tamb = 25°C; GND = 0V

CL = 50pF

VI = 0V or VCC

VI/O = 0V or 3.0V

Outputs disabled

TYPICAL

2.5V

3.3V

4.2

3.0

3.4

2.8

3

3

9

9

40

70

UNIT

ns

pF

pF

µA

ORDERING INFORMATION

PACKAGES

56-Pin Plastic SSOP Type III

56-Pin Plastic TSSOP Type II

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +85°C

74ALVT162823 DL

–40°C to +85°C

74ALVT162823 DGG

NORTH AMERICA

AV162823 DL

AV162823 DGG

DWG NUMBER

SOT371–1

SOT364–1

PIN DESCRIPTION

PIN NUMBER

2, 27

54, 52, 51, 49, 48, 47, 45, 44, 43

42, 41, 40, 38, 37, 36, 34, 33, 31

3, 5, 6, 8, 9, 10, 12, 13, 14

15, 16, 17, 19, 20, 21, 23, 24, 26

56, 29

55, 30

1, 28

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

SYMBOL

1OE, 2OE

1D0-1D8

2D0-2D8

1Q0-1Q8

2Q0-2Q8

1CP, 2CP

1CE, 2CE

1MR, 2MR

GND

VCC

FUNCTION

Output enable input (active-Low)

Data inputs

Data outputs

Clock pulse input (active rising edge)

Clock enable input (active-Low)

Master reset input (active-Low)

Ground (0V)

Positive supply voltage

1998 Aug 27

2

853-2114 19927

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