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R5F2127

SINGLE-CHIP 16-BIT CMOS MCU

Renesas Electronics 

R8C/26 Group, R8C/27 Group

4. Special Function Registers (SFRs)

Table 4.2 SFR Information (2)(1)

Address

0030h

0031h

0032h

Register

Voltage Detection Register 1 (2)

Voltage Detection Register 2 (2)

0033h

0034h

0035h

0036h

Voltage Monitor 1 Circuit Control Register (5)

0037h

0038h

0039h

Voltage Monitor 2 Circuit Control Register (5)

Voltage Monitor 0 Circuit Control Register (6)

Symbol

VCA1

VCA2

After reset

00001000b

• N, D version

• J, K version

00h(3)

00100000b(4)

00h(7)

01000000b(8)

VW1C

VW2C

VW0C

• N, D version

• J, K version

00h

0000X000b(3)

0100X001b(4)

00001000b

0000X000b(7)

0100X001b(8)

003Fh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

Timer RC Interrupt Control Register

Timer RE Interrupt Control Register

Key Input Interrupt Control Register

A/D Conversion Interrupt Control Register

SSU/IIC bus Interrupt Control Register(9)

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer RA Interrupt Control Register

Timer RB Interrupt Control Register

INT1 Interrupt Control Register

INT3 Interrupt Control Register

INT0 Interrupt Control Register

TRCIC

TREIC

KUPIC

ADIC

SSUIC/IICIC

S0TIC

S0RIC

S1TIC

S1RIC

TRAIC

TRBIC

INT1IC

INT3IC

INT0IC

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XXXXX000b

XX00X000b

XX00X000b

XX00X000b

006Fh

0070h

007Fh

X: Undefined

NOTES:

1. The blank regions are reserved. Do not access locations in these regions.

2. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.

(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register.

3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.

4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.

5. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.

(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3.

6. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.

(J, K version) These regions are reserved. Do not access locations in these regions.

7. The LVD1ON bit in the OFS register is set to 1 and hardware reset.

8. Power-on reset, voltage monitor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset.

9. Selected by the IICSEL bit in the PMR register.

Rev.2.10 Sep 26, 2008 Page 18 of 69

REJ03B0168-0210

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