SII150A Ver la hoja de datos (PDF) - Unspecified
Número de pieza
componentes Descripción
Lista de partido
SII150A Datasheet PDF : 6 Pages
| |||
Silicon Image, Inc.
SiI 150A
SiI/DS-0006-C
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Units
TCIP
IDCK Period, 1 Pixel/Clock
FCIP
IDCK Frequency, 1 Pixel/Clock
TCIP
IDCK Period, 2 Pixels/Clock
FCIP
IDCK Frequency, 2 Pixels/Clock
TCIH
IDCK High Time at 112MHz
TCIL
IDCK Low Time at 112MHz
TIJIT
Worst Case IDCK Clock Jitter2,3
TSIDF
Data, DE, VSYNC, HSYNC, and CTL[3:1]
Setup Time to IDCK falling edge
8.93
20
17.8
10
4
4
EDGE = 0
1
50
ns
112
MHz
100
ns
56
MHz
ns
ns
2
ns
ns
THIDF
Data, DE, VSYNC, HSYNC, and CTL[3:1]
EDGE = 0
3
ns
Hold Time from IDCK falling edge
TSIDR
Data, DE, VSYNC, HSYNC, and CTL[3:1]
EDGE = 1
1
ns
Setup Time to IDCK rising edge
THIDR
TDDF
TDDR
THDE
TLDE
SLHT
SHLT
Notes:
Data, DE, VSYNC, HSYNC, and CTL[3:1]
EDGE = 1
3
ns
Hold Time from IDCK rising edge
VSYNC, HSYNC, and CTL[3:1] Delay from DE falling edge1
VSYNC, HSYNC, and CTL[3:1] Delay to DE rising edge1
DE high time1
DE low time1
TCIP
ns
TCIP
ns
8191TCIP
ns
ns
Small Swing Low-to-High
Transition Time
Small Swing High-to-Low
Transition Time
1 Guaranteed by design.
128TCIP
CLOAD = 5pF
0.25 0.3 0.35
ns
RLOAD = 50Ω
REXT_SWING = 510Ω
CLOAD = 5pF
0.25 0.3 0.35
ns
RLOAD = 50Ω
REXT_SWING = 510Ω
2 Jitter can be estimated by 1) triggering a digital scope at the rising of input clock and 2) measuring the peak to peak time spread
of the rising edge of the input clock 1µs after the trigger.
3 Actual jitter tolerance may be higher depending on the frequency of the jitter.
Timing Diagrams
2.0 V
T CIH
T CIP
2.0 V
2.0 V
Revision C
0.8 V
T CIL
Figure 1. Clock Cycle/High/Low Times
0.8 V
SLHT
SHLT
80% VOD
20% VOD
Figure 2. Small Swing Transition Times
3
Subject to Change without Notice
Share Link: 