Silicon Image, Inc.
SiI 161A
SiI-DS-0009-D
Output Timing (continued)
PD
QE[23:0]/QO[23:0],
DE, CTL[3:1],
VSYNC,HSYNC
V IL
TPDL
Figure 5. Output Signals Disabled Timing from PD Active
DE
SCDT
DE
SCDT
TTFSC
TTHSC
Figure 6. SCDT Timing from DE Inactive/Active
Internal
ODCK * 2
ODCK
DE
T
ST
QE[23:0]
FIRST DATA
THIRD DATA
QO[23:0]
SECOND DATA
FOURTH DATA
Figure 7. TFT 2-Pixels/Clock Staggered Output Timing Diagram
Silicon Image, Inc.
8
Subject to Change without Notice