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LPC47M112-MW

Enhanced Super I/O Controller with LPC Interface / Dual Game Port Interface

SMSC -> Microchip 

Enhanced Super I/O Controller with LPC Interface

Datasheet

Table 25 - Interrupt Identification..................................................................................................................................57

Table 26 - Drive Control Delays (ms) ............................................................................................................................58

Table 27 - Effects of WGATE and GAP Bits..................................................................................................................60

Table 28 - Addressing the Serial Port ..........................................................................................................................62

Table 29 - Interrupt Control ..........................................................................................................................................64

Table 30 - Baud Rates..................................................................................................................................................70

Table 31 - Reset Function ............................................................................................................................................72

Table 32 - Register Summary for an Individual UART Channel ...................................................................................72

Table 33 - MPU-401 Host Interface Registers .............................................................................................................77

Table 34 - MIDI Data Port ............................................................................................................................................77

Table 35 - MPU-401 Status Port ..................................................................................................................................78

Table 36 - MIDI Receive Buffer Empty Status Bit.........................................................................................................78

Table 37 - MIDI Transmit Busy Status Bit ....................................................................................................................78

Table 38 – MPU-401 Command Port ...........................................................................................................................79

Table 39 - Parallel Port Connector ...............................................................................................................................83

Table 40 - EPP Pin Descriptions ..................................................................................................................................88

Table 41 - ECP Pin Descriptions...................................................................................................................................90

Table 42 - ECP Register Definitions..............................................................................................................................91

Table 43 - Mode Descriptions .......................................................................................................................................91

Table 44A - Extended Control Register.........................................................................................................................94

Table 45 -Forward Channel Commands (HostAck Low) ..............................................................................................96

Table 46 - PC/AT and PS/2 Available Registers ........................................................................................................100

Table 47 – State of System Pins in Auto Powerdown..................................................................................................100

Table 48 - State of Floppy Disk Drive Interface Pins in Powerdown ..........................................................................100

Table 49 - I/O Address Map........................................................................................................................................106

Table 50 - Host Interface Flags ..................................................................................................................................106

Table 51 - Status Register ..........................................................................................................................................109

Table 52 - Resets .......................................................................................................................................................109

Table 53 - General Purpose I/O Port Assignments ....................................................................................................115

Table 54 - GPIO Configuration Summary ..................................................................................................................117

Table 55 - GPIO Read/Write Behavior .......................................................................................................................117

Table 56 – Different Modes for Fan............................................................................................................................125

Table 57 - Runtime Register Block Summary ............................................................................................................132

Table 58 - Runtime Register Description ...................................................................................................................134

Table 59 - Game Port.................................................................................................................................................155

Table 60 – LPC47M112 Configuration Registers Summary.......................................................................................158

Table 61 - Chip Level Registers .................................................................................................................................161

Table 62 – Logical Device Registers...........................................................................................................................164

Table 63 - I/O Base Address Configuration Register Description.................................................................................166

Table 64 - Interrupt Select Configuration Register Description ....................................................................................167

Table 65 - DMA Channel Select Configuration Register Description............................................................................168

Table 66 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]..................................................169

Table 67 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04].................................................................171

Table 68 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05].................................................................171

Table 69 - KYBD, Logical Device 7 [Logical Device Number = 0x07] .........................................................................172

Table 70 - PME, Logical Device A ..............................................................................................................................173

Table 71 – MPU-401 [Logical Device Number = 0x0B] ...............................................................................................173

SMSC DS – LPC47M112

Page 6

DATASHEET

Rev. 02-16-07

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