AD8305ACP-REEL7(2003) Ver la hoja de datos (PDF) - Analog Devices
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AD8305ACP-REEL7 Datasheet PDF : 20 Pages
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AD8305
GENERAL STRUCTURE
The AD8305 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and will
also be useful in many nonoptical applications. These notes
explain the structure of this unique style of translinear log amp.
Figure 1 is a simplified schematic showing the key elements.
BIAS
GENERATOR
IREF
PHOTODIODE 2.5V
INPUT CURRENT
VREF
IREF
80k⍀
20k⍀
IPD
0.5V
COMM
INPT
VSUM
0.5V
0.5V
Q1
VBE1
Q2
VBE1
VBE2
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T ؋ K
44A/dec
14.2k⍀ 451⍀
VRDZ
VLOG
VBE2 6.69k⍀
VNEG (NORMALLY GROUNDED)
COMM
Figure 1. Simplified Schematic
The photodiode current IPD is received at Pin INPT. The
voltage at this node is essentially equal to those on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts the input
current IPD to a corresponding logarithmic voltage, as shown in
Equation 1. A finite positive value of VSUM is needed to bias
the collector of Q1 for the usual case of a single-supply voltage.
This is internally set to 0.5 V, that is, one fifth of the reference
voltage of 2.5 V appearing on Pin VREF. The resistance at the
VSUM pin is nominally 16 kW; this voltage is not intended as
a general bias source.
The AD8305 also supports the use of an optional negative supply
voltage, VN, at Pin VNEG. When VN is –0.5 V or more negative,
VSUM may be connected to ground; thus INPT and IREF
assume this potential. This allows operation as a voltage-input
logarithmic converter by the inclusion of a series resistor at either
or both inputs. Note that the resistor setting IREF will need to be
adjusted to maintain the intercept value. It should also be noted
that the collector-emitter voltages of Q1 and Q2 are now the full
VN, and effects due to self-heating will cause errors at large
input currents.
The input dependent VBE1 of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. This is gener-
ated externally, to a recommended value of 10 mA. However,
other values over a several-decade range can be used with a
slight degradation in law conformance (TPC 1).
Theory
The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
( ) VBE = kT/qIn IC /IS
(1)
where IC is its collector current, IS is a scaling current, typically
only 10–17 A, and kT/q is the thermal voltage, proportional to
absolute temperature (PTAT) and is 25.85 mV at 300 K. The
current, IS, is never precisely defined and exhibits an even stron-
ger temperature dependence, varying by a factor of roughly a
billion between –35∞C and +85∞C. Thus, to make use of the
BJT as an accurate logarithmic element, both of these tempera-
ture dependencies must be eliminated.
The difference between the base-emitter voltages of a matched pair
of BJTs, one operating at the photodiode current IPD and the second
operating at a reference current IREF, can be written as:
( ) ( ) VBE1 –VBE2 = kT/q In IC /IS – kT/q In IREF /IS
( ) ( ) = In 10 kT/q log10 IPD /IREF
(2)
( )( ) = 59.5mV log10 IPD /IREF T = 300 K
The uncertain and temperature dependent saturation current IS,
which appears in Equation 1, has thus been eliminated. To
eliminate the temperature variation of kT/q, this difference voltage
is processed by what is essentially an analog divider. Effectively, it
puts a variable under Equation 2. The output of this process,
which also involves a conversion from voltage-mode to current-
mode, is an intermediate, temperature-corrected current:
( ) ILOG = IY log10 IPD /IREF
(3)
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (the change in current per
decade). For the AD8305, IY is 44 mA, resulting in a temperature-
independent slope of 44 mA/decade, for all values of IPD and IREF.
This current is subsequently converted back to a voltage-mode
output, VLOG, scaled 200 mV/decade.
It is apparent that this output should be zero for IPD = IREF, and
would need to swing negative for smaller values of input current.
To avoid this, IREF would need to be as small as the smallest
value of IPD. However, it is impractical to use such a small refer-
ence current as 1 nA. Accordingly, an offset voltage is added to
VLOG to shift it upward by 0.8 V when Pin VRDZ is directly
connected to VREF. This has the effect of moving the intercept
to the left by four decades, from 10 mA to 1 nA:
( ) ILOG = IY log10 IPD /IINTC
(4)
where IINTC is the operational value of the intercept current. To
disable this offset, Pin VRDZ should be grounded, then the
intercept IINTC is simply IREF. Since values of IPD < IINTC result in
a negative VLOG, a negative supply of sufficient value is required
to accommodate this situation (discussed later).
The voltage VLOG is generated by applying ILOG to an internal
resistance of 4.55 kW, formed by the parallel combination of a
6.69 kW resistor to ground and the 14.2 kW resistor to the VRDZ
pin. When the VLOG pin is unloaded and the intercept reposi-
tioning is disabled by grounding VRDZ, the output current ILOG
generates a voltage at the VLOG pin of:
VLOG = ILOG ¥ 4.55 k W
( ) = 44 mA ¥ 4.55 k W ¥ log10 IPD/IREF
(5)
( ) = VY log10 IPD/IREF
where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive
loading on VLOG will lower this slope and also result in an
overall scaling uncertainty due to the variability of the on-chip
resistors. Consequently, this practice is not recommended.
VLOG may also swing below ground when dual supplies (VP and
VN) are used. When VN = –0.5 V or larger, the input pins INPT
and IREF may now be positioned at ground level by simply
grounding VSUM.
REV. A
–9–
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