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AD8351 Datasheet PDF : 19 Pages
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AD8351
BALANCE
50Ω
SOURCE
100nF INHI
25Ω
RG
100nF INLO
25Ω
OPHI
25Ω
AD8351
OPLO 25Ω
VOCM
AIN
AD6645
AIN VREF
DIGITAL
OUT
Figure 40. ADC Driving Application Using Differential Input
The circuit of Figure 41 represents a single-ended input to
differential output configuration of the AD8351 driving the
AD6645. In this case, R1 provides the input impedance. RG is
the gain setting resistor. The resistor RF is required to balance
the output voltages required for second-order cancellation by
the AD6645 and can be selected using a chart (see the Single-
Ended-to-Differential Operation section). The circuit depicted
in Figure 41 can provide SFDR performance of better than −90 dBc
with a 10 MHz input and −77 dBc with a 70 MHz input.
RF
SINGLE-
ENDED
50Ω
SOURCE
100nF INHI
R1
25Ω
RG
INLO
25Ω 100nF
OPHI
25Ω
AIN
AD8351
OPLO 25Ω
VOCM
AD6645
AIN VREF
100nF
DIGITAL
OUT
Figure 41. ADC Driving Application Using Single-Ended Input
ANALOG MULTIPLEXING
The AD8351 can be used as an analog multiplexer in applications
where it is desirable to select multiple high speed signals. The
isolation of each device when in a disabled state (PWUP pin
pulled low) is about 60 dBc for the maximum input level of
0.5 V p-p out to 100 MHz. The low output noise spectral density
allows for a simple implementation as depicted in Figure 42.
The PWUP interface can be easily driven using most standard
logic interfaces. By using an N-bit digital interface, up to N devices
can be controlled. Output loading effects and noise need to be
considered when using a large number of input signal paths. Each
disabled AD8351 presents approximately a 700 Ω load in parallel
with the 150 Ω output source impedance of the enabled device.
As the load increases due to the addition of N devices, the
distortion performance will degrade due to the heavier loading.
Distortion better than −70 dBc can be achieved with four devices
muxed into a 1 kΩ load for signal frequencies up to 70 MHz.
BIT 1
SIGNAL
INPUT 1
INHI
PWUP
OPHI
RGP1
RG
AD8351
RGP2
INLO
OPLO
BIT 2
SIGNAL
INPUT 2
INHI
PWUP
OPHI
RGP1
RG
AD8351
RGP2
INLO
OPLO
Data Sheet
N-BIT
DIGITAL
INTERFACE
MUX
OUTPUT
LOAD
BIT N
INHI
PWUP
OPHI
SIGNAL
INPUT N
RG
RGP1
AD8351
RGP2
INLO
OPLO
Figure 42. Using Several AD8351s to Form an N-Channel Analog MUX
I/O CAPACITIVE LOADING
Input or output direct capacitive loading greater than a few
picofarads can result in excessive peaking and/or oscillation
outside the pass band. This results from the package and bond
wire inductance resonating in parallel with the input/output
capacitance of the device and the associated coupling that results
internally through the ground inductance. For low resistive load
or source resistance, the effective Q is lower, and higher relative
capacitance termination or terminations can be allowed before
oscillation or excessive peaking occurs. These effects can be
eliminated by adding series input resistors (RIP) for high source
capacitance, or series output resistors (ROP) for high load
capacitance. Generally less than 25 Ω is all that is required for I/O
capacitive loading greater than ~2 pF. The higher the C, the smaller
the R parasitic suppression resistor required. In addition, RIP helps
to reduce low gain in-band peaking, especially for light resistive
loads.
CSTRAY
RIP
RG
CSTRAY
RIP
ROP
AD8351
ROP
CL
RL
1kΩ
CL
Figure 43. Input and Output Parasitic Suppression Resistors, RIP and ROP,
Used to Suppress Capacitive Loading Effects
Rev. D | Page 14 of 19
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