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AD5382 Datasheet PDF : 40 Pages
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AD5382
Data Sheet
Parameter
LOGIC OUTPUTS (BUSY, SDO)3
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)3
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AVDD
DVDD
Power Supply Sensitivity3
∆Midscale/∆ΑVDD
AIDD
DIDD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
AD5382-31 Unit
Test Conditions/Comments
0.4
DVDD – 0.5
±1
5
V max
V min
μA max
pF typ
Sinking 200 μA
Sourcing 200 μA
SDO only
SDO only
0.4
V max
0.6
V max
±1
μA max
8
pF typ
ISINK = 3 mA
ISINK = 6 mA
2.7/3.6
2.7/5.5
V min/max
V min/max
–85
0.375
0.475
1
20
20
39
dB typ
mA/channel max
mA/channel max
mA max
μA max
μA max
mW max
Outputs unloaded; boost off; 0.25 mA/channel typ
Outputs unloaded; boost on; 0.325 mA/channel typ
VIH = DVDD VIL = DGND
Typically 100 nA
Typically 1 μA
Outputs unloaded; boost off; AVDD = DVDD = 3 V
1 AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.
2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.
3 Guaranteed by characterization, not production tested.
4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded
accuracy specifications.
AC CHARACTERISTICS1
AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND= 0 V.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time2
Slew Rate2
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise 0.1 Hz to 10 Hz
Output Noise Spectral Density
At 1 kHz
At 10 kHz
All Unit
3
μs typ
8
μs max
1.5 V/μs typ
2.5 V/μs typ
12 nV-s typ
15 mV typ
1
nV-s typ
0.8 nV-s typ
0.1 nV-s typ
15 μV p-p typ
40 μV p-p typ
150 nV/√Hz typ
100 nV/√Hz typ
Test Conditions/Comments
1/4 scale to 3/4 scale change settling to ±1 LSB
Boost mode off, CR11 = 0
Boost mode on, CR11 = 1
See the Terminology section
Effect of input bus activity on DAC output under test
External reference, midscale loaded to DAC
Internal reference, midscale loaded to DAC
1 Guaranteed by design and characterization, not production tested.
2 The slew rate can be programmed via the current boost control bit (CR11) in the AD5382 control register.
Rev. D | Page 8 of 40
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