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CS4398CZZR

120 dB, 192 kHz Multi-Bit DAC with Volume Control

Cirrus Logic 

CS4398

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF)

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

-

100

kHz

RST Rising Edge to Start

tirs

500

Bus Free-Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low Time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 10) thdd

0

SDA Setup Time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc, trd

-

Fall Time SCL and SDA

tfc, tfd

-

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

tack

300

-

ns

-

µs

-

µs

-

µs

-

µs

-

µs

-

µs

-

ns

1

µs

300

ns

-

µs

1000

ns

10. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

RST

t irs

S to p

S ta rt

SDA

SCL

t buf

t hdst

t lo w

t high

R e p e ate d

S ta rt

t rd

t hdst

Stop

t fd

t fc

t susp

t hdd

t sud

tack

t sust

t rc

Figure 8. Control Port Timing - I²C Format

DS568F1

15

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