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LAN9221I-ABZJ

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

SMSC -> Microchip 

1.11

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

Datasheet

Host Bus Interface (SRAM Interface)

The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as

an interface for the LAN9221/LAN9221i Control and Status Registers (CSR’s).

The host bus interface is the primary bus for connection to the embedded host system. This interface

models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.

Programmed I/O transactions are supported.

The LAN9221/LAN9221i host bus interface supports 16-bit bus transfers. Internally, all data paths are

32-bits wide. The LAN9221/LAN9221i can be interfaced to either Big-Endian or Little-Endian

processors and includes mixed endian support for FIFO accesses.

Revision 2.9 (03-01-12)

14

DATASHEET

SMSC LAN9221/LAN9221i

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