CY7C4221V-25JC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C4221V-25JC Datasheet PDF : 16 Pages
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CY7C4421V/4201V/4211V/4221V
PRELIMINARY
CY7C4231V/4241V/4251V
Pin Definitions (continued)
Signal Name Description
RCLK
Read Clock
EF
Empty Flag
FF
Full Flag
PAE
Programmable
Almost Empty
PAF
Programmable
Almost Full
RS
Reset
OE
Output Enable
I/O
Description
I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed
into the FIFO.
I Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Electrical Characteristics Over the Operating Range[1]
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
VIL
IIX
IOZL
IOZH
ICC[2]
ISB[3]
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output OFF,
High Z Current
Active Power Supply
Current
Average Standby
Current
Test Conditions
VCC = Min.,
IOH = −2.0 mA
VCC = Min.,
IOL = 8.0 mA
VCC = Max.
OE > VIH,
VSS < VO < VCC
Com’l
Com’l
7C42X1V-15
Min. Max.
2.4
7C42X1V-25
Min. Max.
2.4
7C42X1V- 35
Min. Max. Unit
2.4
V
0.4
0.4
0.4
V
2.0
5.0
2.0
5.0
2.0
5.0
V
−0.5 0.8 −0.5 0.8 −0.5 0.8
V
−10 +10 −10 +10 −10 +10 µA
−10 +10 −10 +10 −10 +10 µA
20
20
20 mA
6
6
6
mA
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
5
pF
7
pF
3
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