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PDM4M4120

1M x 32 CMOS Static RAM Module

Paradigm Technology 

PRELIMINARY

Timing Waveforms of Write Cycle No.1 (WE Controlled)(1,2,3,7)

tWC

ADDRESS

OE

CS

WE

DOUT

DIN

tAW

tAS

tWP(7)

tWR

tWHZ(6)

tOHZ(6)

(4)

tOW(6)

tDW

tDH

Data Valid

PDM4M4120

tOHZ (6)

(4)

Timing Waveforms of Write Cycle No.2 (CS Controlled)(1,2,3,5)

tWC

ADDRESS

tAW

CS

tAS

tCW

tWR

WE

tDW

tDH

DIN

Data Valid

NOTES 1 WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap (tWP) of a LOWCS and a LOWWE.

3. t WR is measured from the earlier ofCS or WE going HIGH to end the write cycle.

4. During this period, I/O pins are in the output state, and input signals must be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs

remain in a high-impedance state.

6. Transition is measured ±200 mV for steady state with a 5 pF load (including scope and jig). This

parameter is determined by device characteristics but is not production tested.

7. If OE is LOW during aWE controlled write cycle, the write pulse width must be the larger of tWP or

(tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW.

If OE is HIGH during aWE controlled write cycle, this requirement does not apply and the write

pulse width can be as short as the specified t WP.

8-58

Rev 2.3

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