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TS4851 Ver la hoja de datos (PDF) - STMicroelectronics

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TS4851 Datasheet PDF : 28 Pages
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TS4851
Electrical Characteristics
Table 9. Electrical characteristics at VCC = +3V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
Parameter
ICC
ISTANDBY
Voo
Vil
Vih
Po
THD + N
SNR
PSRR1
G
Zin
Zin
tes
teh
tel
tds
tdh
tcs
tch
tcl
fclk
Supply Current
Output Mode 7, Vin = 0V,no load
All other output modes, Vin = 0V,no load
Standby Current
Output Mode 0
Output Offset Voltage (differential)
Vin = 0V
“Logic low” input Voltage
“Logic high” input Voltage
Output Power
SPKERout, RL = 8Ω, THD = 1%, F = 1kHz
Rout & Lout, RL = 32Ω, THD = 0.5%, F = 1kHz
Total Harmonic Distortion + Noise
Rout & Lout, Po = 20mW, F = 1kHz, RL = 32
SPKERout, Po = 300mW, F = 1kHz, RL = 8
Rout & Lout, Po = 15mW, 20Hz < F < 20kHz, RL = 32
SPKERout, Po = 250mW, 20Hz < F < 20kHz, RL = 8
Signal To Noise Ratio (A-Weighted)
Power Supply Rejection Ratio2
Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10
Ouput Mode 1
Ouput Mode 2
Ouput Mode 3 (G=+12dB)
Ouput Mode 4 (G=+12dB)
Ouput Mode 5 (G=+12dB)
Ouput Mode 6, 7 (G=+12dB)
Digital Gain Range - Rin & Lin
no load
Digital gain stepsize
Stepsize error
G -22.5dB
G < -22.5dB
Phone In Gain, no load
BTL gain from Phone In to SPKERout
BTL gain from Phone In to Rout & Lout
Phone In Input Impedance 1
Rin & Lin Input Impedance (All Gain Setting) 1
Enable Stepup Time - ENB
Enable Hold Time - ENB
Enable Low Time - ENB
Data Setup Time- DATA
Data Hold Time - DATA
Clock Setup time - CLK
Clock Logic High Time - CLK
Clock Logic Low Time - CLK
Clock Frequency - CLK
1) All PSRR data limits are guaranted by evaluation desgin test.
Min. Typ. Max.
7.5
10
4.5
6.5
0.1
2
5
50
0
0.4
1.4
5
300 340
20
30
0.5
1
0.5
1
86
65
70
54
54
51
53
-34.5
-
+12
1.5
-0.5
+0.5
-1
+1
6
0
15
20
25
37.5
50
62.5
20
20
30
20
20
20
50
50
DC
10
2) Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz
Unit
mA
µA
mV
V
V
mW
%
dB
dB
dB
dB
dB
dB
k
k
ns
ns
ns
ns
ns
ns
ns
ns
MHz
8/28

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