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24C256

256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Fairchild Semiconductor 

DEVICE ADDRESSING

Following a start condition the master must output the address of

the slave it is accessing. The most significant four bits of the slave

address are those of the device type identifier. This is fixed as

1010 for all different FM24C256xxx devices.

The next three bits identify the device address. Address from 000

to 111 are acceptable thus allowing up to eight devices to be

connected to the IIC bus.

The last bit of the slave address defines whether a write or read

condition is requested by the master. A "1" indicates that a READ

operation is to be executed and a "0" initiates the WRITE mode.

A simple review: After the FM24C256xxx recognizes the start

condition, the device interfaced to the IIC bus waits for a slave

address to be transmitted over the SDA line. If the transmitted

slave address matches an address of one of the devices, the

designated slave pulls the SDA line LOW with an acknowledge

signal and awaits further transmissions.

Write Operations

BYTE WRITE

For a WRITE operation, two additional address fields are required

after the control byte acknowledge. These are the word addresses

and comprise fifteen bits to provide access to any one of the 32K

words. The first byte indicates the high-order byte of the word

address. Only the seven least signicant bits can be changed, the

most significant bit is pre-assigned the value "0". Following the

acknowledgement from the first word address, the next byte

indicates the low-order byte of the word address. Upon receipt of

the word address, the FM24C256xxx responds with another

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the

FM24C256xxx begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress, the device's

inputs are disabled and the device will not respond to any requests

from the master. Refer to Figure 5 for the address, acknowledge

and data transfer sequence.

PAGE WRITE

The FM24C256xxx is capable of 64 byte page write operation. It

is initiated in the same manner as the byte write operation; but

instead of terminating the write cycle after the first data word is

transferred, the master can transmit up to 63 more words. After

the receipt of each word, the device responds with an acknowl-

edge.

After the receipt of each word, the internal address counter

increments to the next address and the next SDA data is ac-

cepted. If the master should transmit more than 64 words prior to

generating the stop condition, the address counter will "roll over"

and the previous written data will be overwritten. As with the byte

write operation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 6 for the address, acknowl-

edge and data transfer sequence.

Acknowledge Polling

Once the stop condition is isssued to indicate the end of the host's

write operation, the FM24C256xxx initiates the internal write

cycle. ACK polling can be initiated immediately. This involves

issuing the start condition followed by the slave address for a write

operation. If the FM24C256xxx is still busy with the write opera-

tion, no ACK will be returned. If the device has completed the write

operation, an ACK will be returned and the host can then proceed

with the next read or write operation.

Byte Write (Figure 5)

S

T

Bus Activity: A

Master R

T

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA

S

T

O

P

SDA Line 1 0 1 0

0

Bus Activity

A

A

A

A

C

C

C

C

K

K

K

K

DS800023-8

FM24C256 rev. B.3

8

www.fairchildsemi.com

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