PE3240 Ver la hoja de datos (PDF) - Peregrine Semiconductor
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PE3240 Datasheet PDF : 12 Pages
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PE3240
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Control Interface and Latches (see Figures 6, 7)
fClk
Serial data clock frequency
(Note 1)
tClkH
Serial clock HIGH time
30
tClkL
Serial clock LOW time
30
tDSU
Sdata set-up time to Sclk rising edge
10
tDHLD
Sdata hold time after Sclk rising edge
10
tPW
S_WR pulse width
30
tCWR
Sclk rising edge to S_WR rising edge
30
tCE
Sclk falling edge to E_WR transition
30
tWRC
S_WR falling edge to Sclk rising edge
30
tEC
E_WR transition to Sclk rising edge
30
Main Divider (Including Prescaler)
Fin
Operating frequency
200
PFin
Input level range
External AC coupling
-5
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
20
PFin
Input level range
External AC coupling
-5
Reference Divider
fr
Operating frequency
(Note 3)
Pfr
Reference input power (Note 2)
Single ended input
-2
Phase Detector
fc
Comparison frequency
(Note 3)
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)
100 Hz Offset
Max
Units
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
2200
5
MHz
dBm
220
MHz
5
dBm
100
MHz
dBm
20
MHz
-75
dBc/Hz
1 kHz Offset
-85
dBc/Hz
Note 1:
Note 2:
Note 3:
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Document No. 70-0034-02 │ www.psemi.com
©2006 Peregrine Semiconductor Corp. All rights reserved.
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