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M68AW127BL10NK6

1Mbit (128K x8), 3.0V Asynchronous SRAM

STMicroelectronics 

M68AW127B

REVISION HISTORY

Table 14. Document Revision History

Date

Version

Revision Details

January 2002

1.0

First Issue

09-May-2002

DC Characteristics table clarified (Table 5)

2.0

E1 Controlled, Low VCC Data Retention AC Waveforms clarified (Figure 13)

Low VCC Data Retention Characteristics table clarified (Table 9)

Ordering Information Scheme clarified (Table 13)

01-Jul-2002

3.0

70ns speed class added

SO32 and TSOP32 8x13.4mm package options added

11-Sep-2002

4.0

Commercial code clarified

02-Oct-2002

4.1

Title and header layout modified.

09-Oct-2002

4.2

Commercial code modified.

16-Apr-2003

4.3

Label corrected on “E2 Controlled, Low VCC Data Retention AC Waveforms” figure

21-Aug-2003

4.4

TSOP Package connections modified (Figure 5)

19/20

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