4245 Ver la hoja de datos (PDF) - Peregrine Semiconductor Corp.
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4245 Datasheet PDF : 8 Pages
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Figure 3. Pin Configuration
RF2 1
GND 2
Exposed Solder
Pad - Shorted
to Pin 2
(bottom side)
RF1 3
6 RFC
5 CTRL
4 VDD
Table 2. Pin Descriptions
Pin
Pin
No.
Name
Description
1
RF2
RF2 port (Note 1)
Ground Connection. Traces should be
physically short and connected to the
2
GND
ground plane. This pin is connected to
the exposed solder pad that also must
be soldered to the ground plane for best
performance.
3
RF1
RF1 port (Note 1)
4
VDD
Nominal 3 V supply connection.
CMOS logic level:
5
CTRL
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
6
RFC
Common RF port for switch (Note 1)
Notes: 1. All RF pins must be DC blocked with an external series
capacitor or held at 0 VDC.
Table 3. Operating Ranges
Parameter
Min Typ Max Units
VDD Power Supply Voltage
2.7
3.0
3.3
V
IDD Power Supply Current
VDD = 3V, VCTRL = 3V
250 500
nA
TOP Operating temperature
range
-40
Control Voltage High
0.7x
VDD
Control Voltage Low
85
°C
V
0.3x
VDD
V
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE4245 in the 6-lead 3x3 DFN package is MSL1.
©2003-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
PE4245
Product Specification
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Power supply voltage
-0.3 4.0
V
VI
Voltage on any input
-0.3
VDD+
0.3
V
TST
Storage temperature range -65 150
°C
PIN
Input power (50Ω)
VESD
ESD voltage (Human Body
Model)
30
1500
dBm
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Table 5. Control Logic Truth Table
Control Voltage
Signal Path
CTRL = CMOS High
CTRL = CMOS Low
RFC to RF1
RFC to RF2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Document No. 70-0104-07 │ UltraCMOS™ RFIC Solutions
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