73K324BL-IH Ver la hoja de datos (PDF) - Teridian Semiconductor Corporation
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73K324BL-IH
Teridian Semiconductor Corporation
73K324BL-IH Datasheet PDF : 34 Pages
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73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
DETECT REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
DR RECEIVE
S1
RECEIVE UNSCR. CARR. SPECIAL CALL
SIGNAL
010 LEVEL PATTERN DATA MARK DETECT TONES PROG. QUALITY
INDICATOR DETECT
DETECT
DETECT DETECT INDICATOR
BIT
NAME
CONDITION DESCRIPTION
D0
Signal Quality
0
Indicates normal received signal.
Indicator
1
Indicates low received signal quality (above average
error rate). Interacts with Special Register bits D2, D1.
D1
Call Progress
0
No call progress tone detected.
Detect
1
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in the
normal 350 to 620 Hz call progress bandwidth.
D2
Special Tone
0
Condition not detected.
Detect
1
Condition detected
CR0 D0 TR D0 CR2 D5
1 0 1 2225 Hz ±10 Hz answer tone detected in V.22bis, V.22
modes.
1 1 1 2100 Hz ±21 Hz answer tone detected in V.22 bis, V.22
modes.
0 X 0 900 Hz SCT tone detected in V.23 mode.
1 X 0 2100 Hz or 2225 Hz answer tone detected in QAM,
DPSK mode
D3
Carrier Detect
0
No carrier detected in the receive channel.
1
Indicated carrier has been detected in the received
channel.
D4
Unscrambled
0
No unscrambled mark.
Mark Detect
1
Indicates detection of unscrambled marks in the received
data. Should be time qualified by software.
D5
Receive Data
Continuously outputs the received data stream. This data
is the same as that output on the RXD pin, but it is not
disabled when RXD is tri-stated.
D6
S1 Pattern
0
No S1 pattern being received.
Detect
1
S1 pattern detected. Should be time qualified by
software. S1 pattern is defined as a double di-bit
(001100..) unscrambled 1200 bps DPSK signal. Pattern
must be aligned with baud clock to be detected.
D7
Receive Level
0
Received signal level below threshold, (typical @ -25 dBm0);
Indicator
can use receive gain boost (+18 dB).
1
Received signal above threshold.
Page: 14 of 34
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
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