74ABT16899 Ver la hoja de datos (PDF) - Philips Electronics
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74ABT16899
Philips Electronics
74ABT16899 Datasheet PDF : 16 Pages
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Philips Semiconductors
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
74ABT16899
74ABTH16899
BLOCK DIAGRAM
9–bit
Transparent
Latch
OE
9–bit
Output
Buffer
OEB
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
OEA
SEL
LE
1
Parity
mux
Generator
0
9–bit
Output
Buffer
OE
1
mux
Parity
0
Generator
9–bit
Transparent
Latch
LE
ODD/
EVEN
(1 of 2 parity blocks)
FUNCTION TABLE
INPUTS
OEB OEA SEL LEA
H
H
X
X
H
L
L
L
H
L
L
H
H
L
L
X
H
L
H
X
H
L
H
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
H
H
L
H
H
H
L
L
X
X
H = High voltage level
L = Low voltage level
X = Don’t care
LEB
X
H
H
L
H
H
X
H
X
L
H
X
OPERATING MODE
3-State A bus and B bus (input A & B simultaneously)
B → A, transparent B latch, generate parity from B0 - B7, check B bus parity
B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B → A, transparent B latch, parity feed-through, check B bus parity
B → A, transparent A & B latch, parity feed-through, check A & B bus parity
A → B, transparent A latch, generate parity from A0 - A7, check A bus parity
A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A → B, transparent A latch, parity feed-through, check A bus parity
A → B, transparent A & B latch, parity feed-through, check A & B bus parity
Output to A bus and B bus (NOT ALLOWED)
1998 Feb 25
5
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
LEB
ERRA
ERRB
SH00084
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