74ABT834 Ver la hoja de datos (PDF) - Philips Electronics
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74ABT834 Datasheet PDF : 7 Pages
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Philips Semiconductors Advanced BiCMOS Products
Octal inverting transceiver with parity
generator/checker (3–State)
Objective specification
74ABT834
PIN DESCRIPTION
SYMBOL
PIN NUMBER
A0 – A7
2, 3, 4, 5,
6, 7, 8, 9
B0 – B7
23, 22, 21, 20,
19, 18, 17, 16
OEA
1
OEB
14
PARITY
15
ERROR
10
CLEAR
11
CP
13
GND
12
VCC
24
NAME AND FUNCTION
A port 3–State inputs/outputs
B port 3–State inputs/outputs
Enables the A outputs when Low
Enables the B outputs when Low
Parity output
Error output
Clears the error flag register when Low
Clock input
Ground (0V)
Positive supply voltage
FUNCTION TABLE
MODE
A data to B bus and generate odd parity
output
B data to A bus and check for parity error1
A bus and B bus disabled2
A data to B bus and generate inverted
parity output
OEB
L
H
H
L
OEA
H
L
H
L
INPUTS
An
Σ of Highs
Odd
Even
NA
(output)
X
Odd
Even
Bn + Parity
Σ of Lows
NA
(output)
Odd
Even
X
NA
(output)
An
NA
(input)
Bn
Z
NA
(input)
OUTPUTS
Bn
An
NA
(input)
Z
An
PARITY
H
L
NA
(input)
Z
L
H
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
Internal node
Output
MODE
CLEAR
CP
Bn + Parity
Σ of Lows
Point ”P”
Pre–state
ERRORn–1
Sample
H
↑
H
↑
H
X
Odd
Even
X
H
H
L
X
X
L
Hold
H
↑
X
X
X
Clear
L
X
X
X
X
ERROR
OUTPUT
H
L
L
NC
H
H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
NA = Not applicable
NC = No change
Z = High impedance ”off” state
↑ = Low–to–High clock transition
↑ = Not a Low–to–High clock transition
June 9, 1992
2
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