74AHC86PW Ver la hoja de datos (PDF) - Philips Electronics
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74AHC86PW Datasheet PDF : 16 Pages
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Philips Semiconductors
Quad 2-input EXCLUSIVE-OR gate
Product specification
74AHC86; 74AHCT86
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
• Inputs accepts voltages higher than
VCC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from −40 to +85 °C and
−40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT86 are high-speed
Si-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74AHC/AHCT86 provides the
2-input EXCLUSIVE-OR function.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
SYMBOL PARAMETER
CONDITIONS
tPHL/tPLH
CI
CO
CPD
propagation delay
nA, nB to nY
input capacitance
output capacitance
power dissipation
capacitance
CL = 15 pF;
VCC = 5 V
VI = VCC or GND
VI = VCC or GND
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
TYPICAL
UNIT
AHC AHCT
3.4
3.4
ns
3.0
3.0
pF
4.0
4.0
pF
10
12
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
FUNCTION TABLE
See note 1.
INPUT
nA
nB
L
L
L
H
H
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
OUTPUT
nY
L
H
H
L
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
74AHC86D
74AHC86PW
74AHCT86D
74AHCT86PW
74AHC86D
74AHC86PW DH
74AHCT86D
74AHCT86PW DH
PINS
14
14
14
14
PACKAGES
PACKAGE
MATERIAL
SO
TSSOP
SO
TSSOP
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT108-1
SOT402-1
1999 Sep 17
2
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