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74AHC573D

Octal D-type transparent latch; 3-state

Philips Electronics 

Philips Semiconductors

Octal D-type transparent latch; 3-state

Product specification

74AHC573; 74AHCT573

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A

exceeds 2000 V

MM EIA/JESD22-A115-A

exceeds 200 V

CDM EIA/JESD22-C101

exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt-trigger

actions

• Common 3-state output enable

input

• Functionally identical to the ‘563’

and ‘373’

• Inputs accepts voltages higher than

VCC

• For AHC only:

operates with CMOS input levels

• For AHCT only:

operates with TTL input levels

• Specified from

−40 to +85 and +125 °C.

DESCRIPTION

The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin

compatible with low power Schottky TTL (LSTTL). They are specified in

compliance with JEDEC standard No. 7A.

The 74AHC/AHCT573 are octal D-type transparent latches featuring separate

D-type inputs for each latch and 3-state outputs for bus oriented applications.

A Latch Enable (LE) input and an Output Enable (OE) input are common to all

latches.

The ‘573’ consists of eight D-type transparent latches with 3-state true outputs.

When LE is HIGH, data at the Dn inputs enters the latches. In this condition the

latches are transparent, i.e. a latch output will change state each time its

corresponding D-input changes.

When LE is LOW the latches store the information that was present at the

D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE

is LOW, the contents of the 8 latches are available at the outputs. When OE is

HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE

input does not affect the state of the latches.

The ‘573’ is functionally identical to the ‘533’, ‘563’ and ‘373’, but the ‘533’ and

‘563’ have inverted outputs and the ‘563’ and ‘373’ have a different pin

arrangement.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

CI

CO

CPD

propagation delay

Dn to Qn; LE to Qn

input capacitance

output capacitance

power dissipation

capacitance

CL = 15 pF; VCC = 5 V

VI = VCC or GND

CL = 50 pF; f = 1 MHz;

notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

∑ (CL × VCC2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

TYPICAL

AHC

4.2

AHCT

3.9

3.0

3.0

4.0

4.0

12

18

UNIT

ns

pF

pF

pF

1999 Sep 27

2

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