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74HC597

8-bit shift register with input flip-flops

Philips Electronics 

Philips Semiconductors

8-bit shift register with input flip-flops

Product specification

74HC/HCT597

FEATURES

• 8-bit parallel storage register inputs

• Shift register has direct overriding load and clear

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT597 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT597 consist each of an 8-bit storage

register feeding a parallel-in, serial-out 8-bit shift register.

Both the storage register and the shift register have

positive edge-triggered clocks. The shift register also has

direct load (from storage) and clear inputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/ tPLH

fmax

CI

CPD

propagation delay

SHCP to Q

STCP to Q

PL to Q

maximum clock frequency SHCP

input capacitance

power dissipation capacitance per package

CL = 15 pF; VCC = 5 V

notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

TYPICAL

HC

HCT

UNIT

17

20

ns

25

29

ns

21

26

ns

96

83

MHz

3.5

3.5

pF

29

32

pF

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

2

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