74HC4053 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74HC4053 Datasheet PDF : 32 Pages
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NXP Semiconductors
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logic
Fig 4. Schematic diagram (one switch)
6. Pinning information
6.1 Pinning
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
VCC
VEE
Y
VCC
VEE
VCC
VCC
VEE
Z
001aad544
2Y1 1
2Y0 2
3Y1 3
3Z 4
3Y0 5
E6
VEE 7
GND 8
74HC4053
74HCT4053
16 VCC
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
9 S3
001aae127
74HC4053
74HCT4053
terminal 1
index area
2Y0 2
3Y1 3
3Z 4
3Y0 5
E6
VEE 7
VCC(1)
15 2Z
14 1Z
13 1Y1
12 1Y0
11 S1
10 S2
001aae128
Transparent top view
Fig 5.
Pin configuration DIP16, SO16, and (T)SSOP16
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 6. Pin configuration DHVQFN16
74HC_HCT4053
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 July 2012
© NXP B.V. 2012. All rights reserved.
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