74LVC1G17 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVC1G17 Datasheet PDF : 21 Pages
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NXP Semiconductors
74LVC1G17
Single Schmitt trigger buffer
A
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
74LVC1G17
n.c. 1
A2
5 VCC
GND 3
4Y
001aaf190
Fig 4. Pin configuration SOT353-1 and SOT753
74LVC1G17
n.c. 1
A2
6 VCC
5 n.c.
GND 3
4Y
001aaf402
Transparent top view
Fig 6. Pin configuration SOT891, SOT1115 and
SOT1202
6.2 Pin description
Table 3.
Symbol
n.c.
A
GND
Y
VCC
Pin description
Pin
TSSOP5 and X2SON5
1
2
3
4
5
XSON6
1, 5
2
3
4
6
Y
mnb152
74LVC1G17
n.c. 1
6 VCC
A2
5 n.c.
GND 3
4Y
001aaf191
Transparent top view
Fig 5. Pin configuration SOT886
74LVC1G17
n.c. 1
3
GND
5 VCC
A2
4Y
aaa-003025
Transparent top view
Fig 7. Pin configuration SOT1226 (X2SON5)
Description
not connected
data input
ground (0 V)
data output
supply voltage
74LVC1G17
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 29 June 2012
© NXP B.V. 2012. All rights reserved.
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