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74VHC373M

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

STMicroelectronics 

®

74VHC373

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT NON INVERTING

s HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA = 25 oC

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s POWER DOWN PROTECTION ON INPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 373

s IMPROVED LATCH-UP IMMUNITY

s LOW NOISE: VOLP = 0.9V (Max.)

DESCRIPTION

The 74VHC373 is an advanced high-speed

CMOS OCTAL D-TYPE LATCH with 3 STATE

OUTPUT NON INVERTING fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology.

This 8 bit D-Type latch is controlled by a latch

enable input (LE) and an output enable input

(OE).

M

(Micro Package)

T

(TSSOP Package)

ORDER CODES :

74VHC373M

74VHC373T

While the LE input is held at a high level, the Q

outputs will follow the data inputs precisely. When

the LE is taken low, the Q outputs will be latched

precisely at the logic level of D input data. While

the (OE) input is low, the 8 outputs will be in a

normal logic state (high or low logic level) and

while high level the outputs will be in a high

impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 1999

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