70P2352-IGT Ver la hoja de datos (PDF) - Unspecified

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Lista de partido

70P2352-IGT

Dual Channel OC-3/ STM1-E/ E4 LIU

Unspecified 

78P2352

Dual Channel

OC-3/ STM1-E/ E4 LIU

PIN DESCRIPTION (CONTINUED)

RECEIVER PINS

NAME

POx0D

POx1D

POx2D

POx3D

POxCK

SOxDP

SOxDN

SOxCKP

SOxCKN

RXxP

RXxN

PIN TYPE DESCRIPTION

46, 51

45, 52

42, 55

41, 56

38, 59

28, 69

29, 68

25, 72

26, 71

Receive (Parallel Mode) Data Output:

Recovered receive data deserialized into four-bit CMOS parallel (nibble)

CO outputs. The MSB (POx3D) is received first. Active, but undefined during

reset.

Note: During Loss of Signal conditions, data outputs are held low.

Receive (Parallel Mode) Clock Output:

A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by

CO

dividing down the recovered receive clock. By default, receive data is

clocked out on the falling edge. Active during reset.

Note: During Loss of Signal conditions, the clock will remain on the last

divided down phase selection of the Rx DLL and output a steady clock.

Receive (Serial Mode) Data Output:

PO

Recovered receive serial NRZ data at LVPECL levels. Active, but undefined

during reset.

Note: During Loss of Signal conditions, data outputs are held at logic 0.

Receive (Serial Mode) Clock Output:

Recovered receive serial clock. By default, recovered serial NRZ data is

PO clocked out the falling edge of SOxCKP. Active during reset.

Note: During Loss of Signal conditions, the clock will remain on the last

phase selection of the Rx DLL and output a steady clock.

118, 107 A/ Receiver CMI or LVPECL Input:

119, 106

PI

The input is either transformer-coupled to coaxial cable for CMI data or AC-

coupled at LVPECL levels to an optical transceiver module for NRZ data.

Page: 17 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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