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82077AA-1

CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER

Intel 

82077AA

NOTE

PS0 1 are 8272A control signals but are not available as outputs on the 82077AA

Figure 3-3 Precompensation Block Diagram

290166 – 6

3 2 4 REFERENCE FILTER

To provide a clean bias voltage for the internal data

separator two pins have been provided to filter this

signal It is recommended to place a 0 0047 uF ca-

pacitor between HIFIL and LOFIL to filter the refer-

ence signal A smaller capacitance will reduce the

effectiveness of the filter and could result in a lower

jitter tolerance Conversely a larger capacitance has

the potential to further improve jitter tolerance but

will result in an increased settling time after a

change in data rate For instance a filter capacitor

of 0 005 uF will yield a settling time of approximately

500 microseconds Since HIFIL generates a relative-

ly low current signal (approximately 10 uA) care also

needs to be taken to avoid external leakage on this

pin The quality of the capacitor solder flux grease

and dirt can all impact the amount of leakage on the

board

3 3 Write Precompensation

The write precompensation logic is used to minimize

bit shifts in the RDDATA stream from the disk drive

The shifting of bits is a known phenomena of mag-

netic media and is dependent upon the disk media

AND the floppy drive

The 82077AA monitors the bit stream that is being

sent to the drive The data patterns that require pre-

compensation are well known Depending upon the

pattern the bit is shifted either early or late (or not at

all) relative to the surrounding bits Figure 3-3 is a

block diagram of the internal circuit

shift register is clocked at the main clock rate

(24 MHz) The output is fed into 2 multiplexors one

for early and one for late A final stage of multiple-

xors combines the early late and normal data

stream back into one which is the WRDATA output

4 0 CONTROLLER PHASES

For simplicity command handling in the 82077AA

can be divided into three phases Command Execu-

tion and Result Each phase is described in the fol-

lowing secions

4 1 Command Phase

After a reset the 82077AA enters the command

phase and is ready to accept a command from the

host For each of the commands a defined set of

command code bytes and parameter bytes has to

be written to the 82077AA before the command

phase is complete (Please refer to Section 5 0 for

the command descriptions) These bytes of data

must be transferred in the order prescribed

Before writing to the 82077AA the host must exam-

ine the RQM and DIO bits of the Main Status Regis-

ter RQM DIO must be equal to ‘‘1’’ and ‘‘0’’ respec-

tively before command bytes may be written RQM is

set false by the 82077AA after each write cycle until

the received byte is processed The 82077AA as-

serts RQM again to request each parameter byte of

The top block is a 13-bit shift register with the no

delay tap being in the center This allows 6 levels of

early and late shifting with respect to nominal The

15

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