82C85 Ver la hoja de datos (PDF) - Intersil

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82C85

CMOS Static Clock Controller/Generator

Intersil 

Timing Waveforms (Continued)

82C85

CLK

RDY1, 2

AEN1, 2

ASYNC

(9)

TCLRIX

(6)

TRIVCL

(12) TA1VRIV

(10)

TAYVCL

TCLAYX

(11)

(9)

TCLR1X

(8)

TRILCL

TCLA1X (13)

READY

(35)

TRYHCH

(34)

TRYLCL

FIGURE 9. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES)

EFI

CLK

CLK50

TSTOP

(24)

(SEE NOTE)

PCLK

S0

(18)

TSVCH

S1

S2/STOP

(18)

TSVCH

TCHSX (19)

TCHSX (19)

RES

START

TRSVCH (20)

FIGURE 10. CLOCK STOP (F/C HIGH OR F/C LOW)

NOTE: When F/C is low, CLK and CLK50 stop high. When F/C is high, CLK and CLK50 may stop either high or low.

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