87C552 Ver la hoja de datos (PDF) - Philips Electronics
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87C552
Philips Electronics
87C552 Datasheet PDF : 24 Pages
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Philips Semiconductors
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Product specification
87C552
AC ELECTRICAL CHARACTERISTICS1, 2
12MHz CLOCK 16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX MIN MAX
MIN
MAX
1/tCLCL
2
tLHLL
2
tAVLL
2
tLLAX
2
tLLIV
2
tLLPL
2
tPLPH
2
tPLIV
2
tPXIX
2
tPXIZ
2
tAVIV
2
tPLAZ
2
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
3.5
16
127
85
2tCLCL–40
28
8
tCLCL–55
48
28
tCLCL–35
234
150
4tCLCL–100
43
23
tCLCL–40
205
143
3tCLCL–45
145
83
3tCLCL–105
0
0
0
59
38
312
208
10
10
tCLCL–25
5tCLCL–105
10
tAVLL
3, 4 Address valid to ALE low
43
23
tCLCL–40
tRLRH
3
RD pulse width
400
275
6tCLCL–100
tWLWH
3
WR pulse width
400
275
6tCLCL–100
tRLDV
3
RD low to valid data in
252
148
tRHDX
3
Data hold after RD
0
0
0
tRHDZ
3
Data float after RD
97
55
tLLDV
3
ALE low to valid data in
517
350
tAVDV
3
Address to valid data in
585
398
tLLWL
3, 4 ALE low to RD or WR low
200
300
138
238
3tCLCL–50
tAVWL
3, 4 Address valid to WR low or RD low
203
120
4tCLCL–130
tQVWX
4
Data valid to WR transition
23
3
tCLCL–60
tDW
4
Data before WR
433
288
7tCLCL–150
tWHQX
4
Data hold after WR
33
13
tCLCL–50
tRLAZ
4
RD low to address float
0
0
tWHLH
3, 4 RD or WR high to ALE high
43
123
23
103
tCLCL–40
External Clock
tCHCX
5
High time3
20
20
20
tCLCX
5
Low time3
20
20
20
tCLCH
5
Rise time3
20
20
tCHCL
5
Fall time3
20
20
Serial Timing – Shift Register Mode4 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0V; Load Capaciatnce = 80pF)
tXLXL
6
Serial port clock cycle time
1.0
0.75
12tCLCL
tQVXH
6
Output data setup to clock rising edge 700
492
10tCLCL–133
tXHQX
6
Output data hold after clock rising edge 50
8
2tCLCL–117
tXHDX
6
Input data hold after clock rising edge
0
0
0
tXHDV
6
Clock rising edge to input data valid
700
492
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 83.3ns at fOSC = 12MHz.
tCLCL = 62.5ns at fOSC = 16MHz.
4. These values are characterized but not 100% production tested.
5tCLCL–165
2tCLCL–70
8tCLCL–150
9tCLCL–165
3tCLCL+50
0
tCLCL+40
20
20
10tCLCL–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
1998 May 01
11
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