USB97CFDC-MN Ver la hoja de datos (PDF) - SMSC -> Microchip
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USB97CFDC-MN Datasheet PDF : 20 Pages
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t1
FA[0:19
]
FD[7:0
nFRD
nFW R
t3
t2
t5
t4
FIGURE 2 – FLASH READ TIMING
Table 3 – Flash Read Timing
NAME
PARAMETER
MIN TYP MAX
t1 FA[14:0] Address setup time to nFRD asserted
40
t2 nFRD pulse width
110
t3 FD[7:0] Data setup time to nFRD de-asserted
30
t4 FD[7:0] Data hold time from nFRD de-asserted
0
t5 FA[14:0] Address hold time from nFRD de-asserted 35
UNITS
ns
ns
ns
ns
ns
t1
S A [1 3 :0
S D [7:0
nMEMW
t3
t2
t5
t4
FIGURE 3 – SRAM MEMORY WRITE TIMING
NAME
t1
t2
t3
t4
t5
Table 4 – SRAM Memory Write Timing
PARAMETER
MIN
SA[19:0] valid before nMEMWR asserted
10
nMEMWR pulse width
100
SD[7:0] Data setup time to nMEMWR de-asserted
50
SD[7:0] Data hold time from nMEMWR de-asserted
10
nMEMWR de-asserted to SA[13:0] invalid
10
TYP MAX
UNITS
ns
ns
ns
ns
ns
SMSC DS – USB97CFDC
Page 13
Rev. 12/15/2000
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