97CFDC Ver la hoja de datos (PDF) - SMSC -> Microchip
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97CFDC Datasheet PDF : 20 Pages
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t1
S A [13:0
S D[7:0]
nM E M R
t3
t2
t5
t4
FIGURE 4 - SRAM MEMORY READ TIMING
Table 5 – SRAM Memory Read Timing
NAME
PARAMETER
MIN TYP MAX
t1 SA[19:0] valid before nMEMRD asserted
10
t2 nMEMRD pulse width
100
t3 SD[7:0] Data setup time to nMEMRD de-asserted
50
t4 SD[7:0] Data hold time from nMEMRD de-asserted
20
t5 nMEMRD de-asserted to SA [13:0] invalid
10
UNITS
ns
ns
ns
ns
ns
nDIR
nSTEP
nDS0
nINDEX
nRDATA
nWDATA
t3
t4
t1
t2
t5
t6
t7
t8
NAME
PARAMETER
MIN
t1
nDIR Set Up to nSTEP Low
t2
nSTEP Active Time Low
t3
nDIR Hold Time After nSTEP
t4
nSTEP Cycle Time
t5
nDS0-1 Hold Time from nSTEP Low
t6
nINDEX Pulse Width
t7
nRDATA Active Time Low
t8
nWDATA Write Data Width Low
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz)
WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz)
TYP
4
24
96
132
20
2
40
.5
MAX
UNITS
X*
X*
X*
X*
X*
X*
ns
Y*
FIGURE 5 - DISK DRIVE TIMING
SMSC DS – USB97CFDC
Page 14
Rev. 12/15/2000
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