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A25L16PMF-50U

8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface

AMIC Technology 

A25L80P

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new

values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN)

instruction has been decoded and executed, the device sets

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by

driving Chip Select ( S ) Low, followed by the instruction code

and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 7. The Write

Status Register (WRSR) instruction has no effect on b6, b5, b1

and b0 of the Status Register. b6 and b5 are always read as 0.

Chip Select ( S ) must be driven High after the eighth bit of the

data byte has been latched in. If not, the Write Status Register

(WRSR) instruction is not executed. As soon as Chip Select ( S )

is driven High, the self-timed Write Status Register cycle

(whose duration is tW) is initiated. While the Write Status

Register cycle is in progress, the Status Register may still be

read to check the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self-timed Write

Status Register cycle, and is 0 when it is completed. When the

cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user

to change the values of the Block Protect (BP2, BP1, BP0) bits,

to define the size of the area that is to be treated as read-only,

as defined in Table 1. The Write Status Register (WRSR)

instruction also allows the user to set or reset the Status

Register Write Disable (SRWD) bit in accordance with the

Write Protect ( W ) signal. The Status Register Write Disable

(SRWD) bit and Write Protect ( W ) signal allow the device to

be put in the Hardware Protected Mode (HPM). The Write

Status Register (WRSR) instruction is not executed once the

Hardware Protected Mode (HPM) is entered.

Figure 7. Write Status Register (WRSR) Instruction Sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

Status

Register In

D

7654 3210

Q

High Impedance

MSB

PRELIMINARY (May 2005, Version 0.0)

11

AMIC Technology Corp.

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