A25L80PMF-50UF Ver la hoja de datos (PDF) - AMIC Technology
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A25L80PMF-50UF Datasheet PDF : 34 Pages
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A25L80P
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising edge of
Serial Clock (C) after Chip Select ( S ) is driven Low. Then, the
one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Status Register (RDSR) or
Release from Deep Power-down, Read Device Identification
and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip
Select ( S ) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select ( S ) must be driven High exactly at a
byte boundary, otherwise the instruction is rejected, and is not
executed. That is, Chip Select ( S ) must driven High when the
number of clock pulses after Chip Select ( S ) being driven Low
is an exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
Table 3. Instruction Set
Instruction
Description
One-byte Instruction Code
WREN
Write Enable
0000 0110
06h
WRDI
Write Disable
0000 0100
04h
RDSR
Read Status Register
0000 0101
05h
WRSR
Write Status Register
0000 0001
01h
READ
Read Data Bytes
0000 0011
03h
FAST_READ Read Data Bytes at Higher Speed
0000 1011
0Bh
PP
Page Program
0000 0010
02h
SE
Sector Erase
1101 1000
D8h
BE
Bulk Erase
1100 0111
C7h
DP
Deep Power-down
1011 1001
B9h
RDID
Read Device Identification
1001 1111
9Fh
Release from Deep Power-down,
RES
and Read Electronic Signature
1010 1011
ABh
Release from Deep Power-down
Address
Bytes
0
0
0
0
3
3
3
3
0
0
0
0
0
Dummy
Bytes
0
0
0
0
0
1
0
0
0
0
0
3
0
Data Bytes
0
0
1 to ∞
1
1 to ∞
1 to ∞
1 to 256
0
0
0
1 to 3
1 to ∞
0
PRELIMINARY (May 2005, Version 0.0)
8
AMIC Technology Corp.
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