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A25L40PTN-UF

4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface

AMIC Technology 

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 4.) sets the

Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every

Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and

Write Status Register (WRSR) instruction.

A25L40P Series

The Write Enable (WREN) instruction is entered by driving

Chip Select ( S ) Low, sending the instruction code, and then

driving Chip Select ( S ) High.

Figure 4. Write Enable (WREN) Instruction Sequence

S

01 23 45 67

C

Instruction

D

High Impedance

Q

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 5.) resets the

Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip

Select ( S ) Low, sending the instruction code, and then driving

Chip The Write Enable Latch (WEL) bit is reset under the

following conditions:

﹣ Power-up

﹣ Write Disable (WRDI) instruction completion

﹣ Write Status Register (WRSR) instruction completion

﹣ Page Program (PP) instruction completion

﹣ Sector Erase (SE) instruction completion

﹣ Bulk Erase (BE) instruction completion

Figure 5. Write Disable (WRDI) Instruction Sequence

S

01 23 45 67

C

Instruction

D

High Impedance

Q

PRELIMINARY (May, 2007, Version 0.4)

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AMIC Technology Corp.

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