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A25L40PTQ-UF

4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface

AMIC Technology 

Sector Erase (SE)

The Sector Erase (SE) instruction sets all bits to 1 (FFh).

Before it can be accepted, a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the

Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip

Select ( S ) Low, followed by the instruction code on Serial

Data Input (D). Chip Select ( S ) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 13. Chip Select

( S ) must be driven High after the eighth bit of the instruction

code has been latched in, otherwise the Sector Erase

Figure 13. Sector Erase (SE) Instruction Sequence

A25L40P Series

instruction is not executed. As soon as Chip Select ( S ) is

driven High, the self-timed Sector Erase cycle (whose

duration is tBE) is initiated. While the Sector Erase cycle is in

progress, the Status Register may be read to check the value

of the Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Sector Erase cycle, and is

0 when it is completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Sector Erase (SE) instruction is executed only if all Block

Protect (BP2, BP1, BP0) bits are 0. The Sector Erase (SE)

instruction is ignored if one, or more, sectors are protected.

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

Instruction

24-Bit Address

D

23 22 21 3 2 1 0

MSB

Notes: Address bits A23 to A19 are Don’t Care.

PRELIMINARY (May, 2007, Version 0.4)

17

AMIC Technology Corp.

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