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A25L40PTN-50UF

4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface

AMIC Technology 

A25L40P Series

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only

way to put the device in the lowest consumption mode (the

Deep Power-down mode). It can also be used as an extra

software protection mechanism, while the device is not in

active use, since in this mode, the device ignores all Write,

Program and Erase instructions.

Driving Chip Select ( S ) High deselects the device, and puts

the device in the Standby mode (if there is no internal cycle

currently in progress). But this mode is not the Deep

Power-down mode. The Deep Power-down mode can only be

entered by executing the Deep Power-down (DP) instruction,

to reduce the standby current (from ICC1 to ICC2, as specified in

DC Characteristics Table.).

Once the device has entered the Deep Power-down mode, all

instructions are ignored except the Release from Deep

Power-down and Read Electronic Signature (RES) instruction.

This releases the device from this mode. The Release from

Deep Power-down and Read Electronic Signature (RES)

instruction also allows the Electronic Signature of the device

to be output on Serial Data Output (Q).

The Deep Power-down mode automatically stops at

Power-down, and the device always Powers-up in the

Standby mode.

The Deep Power-down (DP) instruction is entered by driving

Chip Select ( S ) Low, followed by the instruction code on

Serial Data Input (D). Chip Select ( S ) must be driven Low for

the entire duration of the sequence. The instruction sequence

is shown in Figure 15.

Chip Select ( S ) must be driven High after the eighth bit of the

instruction code has been latched in, otherwise the Deep

Power-down (DP) instruction is not executed. As soon as

Chip Select ( S ) is driven High, it requires a delay of tDP

before the supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an Erase,

Program or Write cycle is in progress, is rejected without

having any effects on the cycle that is in progress.

Figure 15. Deep Power-down (DP) Instruction Sequence

S

tDP

01 2 3 45 6 7

C

Instruction

D

Stand-by Mode

Deep Power-down Mode

PRELIMINARY (May, 2007, Version 0.4)

19

AMIC Technology Corp.

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