![](/html/AMICC/254363/page30.png)
Figure 21. Serial Input Timing
S
tCHSL
C
tDVCH
D
tSLCH
tCHDX
MSB IN
High Impedance
Q
A25L40P Series
tCHSH
tSHSL
tSHCH
tCLCH
LSB IN
tCHCL
Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W
tWHSL
S
C
tSHWL
D
High Impedance
Q
PRELIMINARY (May, 2007, Version 0.4)
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AMIC Technology Corp.